1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to the compensation of a delay (i.e., skew) in the propagation of signals via different signal paths, and more particularly, to a circuit for compensating for a delay in the propagation of multi-bit width data signals between large-scale integrated (LSI) circuits or between modules.
2. Description of the Related Art
As the operating speed of central processing units (CPUs), memories, and large-scale integrated (LSI) circuits increase, the demand for high-speed transmission of signals between LSI circuits or between modules has steadily grown. In order to transmit large amounts of data, methods of transmitting data using a number of multi-bit data transmission paths in parallel have been widely used.
However, in the case of transmitting data using a multi-bit data transmission system, a delay in the propagation of a plurality of signals, including a clock signal, a reset signal, and a data signal, via a plurality of signal paths, i.e., skew, is highly likely to occur if the signal paths have different printed circuit board (PCB) trace characteristics and different lengths and, thus, result in different data propagation speeds. Because of skew, multi-bit data transmitted at the same time by a transmitting party may be received by a receiving party at different times.
As the speed of data transmission increases, the proportion of data imbalance caused by skew to the period of data signals increases. Thus, a plurality of signals that need to be received at the same time may not be received at the same time. Therefore, it is necessary to develop deskew circuits that are capable of guaranteeing a stable reception of data by compensating for the skew.
An example of a skew compensation technique is disclosed in Japanese Patent Laid-Open Gazette No. 1998-040071 (hereinafter referred to as Cited Reference 1) entitled “Arithmetic Device and Method of Controlling Time Delay Therein.”
In detail, Cited Reference 1 discloses an arithmetic device which includes two arithmetic circuits that perform an operation, at least two arithmetic termination circuits that determine whether the arithmetic circuits have completed their operations, and a synthesizer that receives an arithmetic termination signal obtained by each of the arithmetic termination circuits and determines whether all the arithmetic circuits have completed their operations.
The arithmetic device also includes a synchronization clock generation circuit which generates a clock signal that drives the arithmetic circuits to operate in synchronization with the arithmetic termination circuit. Therefore, after the arithmetic circuits terminate their operations, they sequentially perform their operations according to the clock signal, thereby preventing data deviation caused by skew.
According to Cited Reference 1, an input clock signal CLK and an input reset signal RESET are provided to each of first and second arithmetic circuits via a corresponding buffer circuit, as illustrated in FIG. 1. In this case, the input clock signal CLK and the input reset signal RESET must have the same phase, and buffer circuits with high driving power are needed.
However, the invention disclosed in Cited Reference 1 may result in an increase in the power consumption of buffer circuits that output a clock signal and a reset signal, especially when the aforementioned synchronization design is applied to LSI circuits. In addition, in some cases, buffer circuits which supply a clock signal and a reset signal consume more power than the arithmetic circuits that perform data processing operations.